1. Field of the Invention
The present invention relates to an address release method and to a common buffering device for an ATM (asynchronous transfer mode) switching system which employs the address release method.
2. Related Arts
An ATM switching system, which employs a common buffering device, manages for each output highway (HW) a write address and a read address which are used by the buffering device to implement a process for the switching of cells.
In FIG. 10 is an example arrangement for a common buffering device included in an ATM switching system. A cell buffering module 1 is connected to a highway line side via highway interfaces 5 and 6.
In the cell buffer module 1, a centrally located cell buffer memory consists of 16 buffer memories MEM0 to MEM15, and multiplexers (MUX) 100 to 115 and demultiplexers (DMUX) 200 to 215, which are included in a number equivalent to the buffer memory count.
A write controller 2 and a read controller 3 are included as common buffer controllers, and an address buffer memory 4 is provided in association with the write controller 2 and the read controller 3.
Each cell in the cell buffer memory has a capacity of 128K, and holds ATM cells stored in a bit slice form. Further, each bit of the 16 parallel bit sets constituting the ATM cell corresponds to one of the 16 buffer memories MEM0 to MEM15 which form the cell buffer memory.
Since in an ATM cell there are 64 bytes, if it is arranged into 16 parallel bit forms, its 32 clock width is the equivalent of the time for one cell. For bit slicing, a data set of 32 bits per clock, which is obtained by developing individual bits in parallel, is employed as the unit of control for processing.
That is, in FIG. 10, the ATM cell transmitted across each highway line for the highway interface 5 is divided into 16 bit slices each of which has a 32 bit width. The bit slices having the 32 bit widths are transmitted in parallel to the cell buffer module 1.
In the cell buffer module 1, identically numbered bits of the bit slices received in parallel are multiplexed by the multiplexers MUX. That is, in FIG. 10, for example, of the 16 bit slices the multiplexer (MUX) 100 multiplexes the 1st bit which corresponds to the first bit of an ATM cell, and the multiplexer (MUX) 115 multiplexes the 16th bit slice.
The bit slices multiplexed by the multiplexers (MUX) 100 to 115 are stored in parallel in the 16 buffer memories MEM0 to MEM15 for corresponding bits. The storage address is set by the write controller 2 of the common buffer controller.
The storage address set by the write controller 2 is stored in the address buffer memory 4. The read controller 3 of the common buffer controller provides, as a read address, an address which corresponds to a write address, and 16 bit slices having a 32 bit width are read in parallel from the read address.
The 16 bit slices read in parallel are separated by the demultiplexers (DMUX) 200 to 215, and are transmitted via the highway interface 6 to the destination lines.
FIG. 11 is a diagram for explaining the procedures performed by the write controller 2 for setting and releasing the storage addresses. In FIG. 11, the ATM cells from the multiplexers (MUX) 100 to 115 are input (step SO) and TAG information for the cells is analyzed by the write controller 2, and an empty address xcex1 is defined as a write address xcex1 (step S1) and is written in the address buffer memory 4.
Then, the cell data are written at the write address xcex1, which is set in the memories MEM0 to MEM14 in the cell buffer module 1 (step S2). The write controller 2 transmits as a read address the write address to the read control circuits RC1 to RCn, of the read controller 3, which correspond to the highway lines along which cell data to be read from the TAG information for the cell 100 is written to the address xcex1 (step S3).
The read control circuits RC1 to RCn of the read controller 3 sequentially write received read addresses in the FIFO memory. The read control circuits RC1 to RCn then access read addresses a set by corresponding lines in the order in which they are written, and read the cell data therefrom (step S4).
The read control circuits RC1 to RCn further notify the write controller 2 of the read address xcex1 at which cell data has been read (step S5).
Upon receipt of the read address xcex1, the write controller 2 deletes and releases a corresponding write address xcex1 from the address buffer memory 4 (step S6).
As is described above, the write address of the cell buffer module 1 is released when the ATM cell is read from the buffer memories MEM0 to MEM15 by the read controller 3 and is transmitted to the highway line. The released address is stored as a write address for the ATM cell which will arrive next.
When the reading is performed along a specific line, and when the ATM cell is read from the buffer memory MEM0 to MEM15 and is transmitted to the line, the write address of the buffer module 1 is released and is stored as a write address for the ATM cell which will arrive next. In the conventional system, a problem will arise when the received ATM cell is a multi-address call for transmitting the same cell to a plurality of lines.
Specifically, when the ATM cell is a multi-address communication call, releasing the address is not a simple operation, even when the ATM cell is read from a specific line. The address can not be released unless the reading is completed for all the lines for which the ATM cell should be copied. To resolve this problem, various methods have been proposed.
As previously described, as its depth the cell buffer module 1 in FIG. 10 has a capacity of 128K. Accordingly, the address buffer memory 4 has a large capacity. Therefore, while taking into account how the common buffer device which uses an LSI (large scale integration) is formed, providing such a large memory in the LSI is not advantageous.
An effective method by which this can be effected is for the large memory to be constituted by using an external memory. However, when this is done, another problem arises as a result of the difference in the access speed of the external memory and the signal processing speed of the LSI.
It is, therefore, one objective of the present invention to provide an address release method whereby, with a simple arrangement for which a high-speed memory is employed, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call, and a common buffering device can be used for an ATM switching system which employs this address release method.
To achieve the above objective, according to one aspect of the present invention, a method for releasing an address in a common buffering device includes the steps of:
setting for an ATM cell which is to be transmitted to a specific line a write address for the common buffer memory;
writing the ATM cell at the write address;
reading the ATM cell from an address which corresponds to the write address;
transmitting the ATM cell to the specific line; and
releasing the write address in the common buffering device.
Furthermore, as the feature of the present invention, in a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the plurality of multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
According to another aspect of the present invention, when the destination line for the transmission of the ATM cell in the read control table does not match the plurality of multi-address lines set in the write control table, to update the read control table, a line to which the ATM cell has been transmitted is added to the read control table.
According to an additional aspect of the present invention, in a write table are entered a plurality of multi-address lines across which is multicast an ATM cell written at a specific address in the common buffering device. A check is performed in advance to determine whether the same read addresses are present that have occurred during the period of time allocated for one cell, and bit sets are generated in the read control table. Each time the ATM cell is read from the specific address, a corresponding bit set in the read control table is compared with the plurality of multi-address lines set in the write control table. When the bit set and the lines match, the write address which is set in the write control table for the ATM cell is released.
According to a further aspect of the present invention, the bit set is acquired by sequentially determining whether a read address for each adjacent read line is matched.
The basic structure of a common buffering device, which employs the above described address release method, comprises:
a common buffer memory;
a write controller for setting in the common buffer memory an address to which an ATM cell which is to be transmitted to a predetermined line is to be written;
a read controller for reading the ATM cell from the address set by the write controller, and for transmitting the ATM cell to a corresponding line;
a write control table wherein is set a plurality of multi-address communication lines to which are multicast an ATM cell read from a specific address in the common buffering device; and
a read control table for, each time the ATM cell is read for which the plurality of multi-address communication lines are set, setting a destination line to which the ATM cell is to be transmitted.
According to still another aspect of the present invention, the write controller compares the multi-address lines in the write control table with the line which is set in the read control table and to which the ATM cell is to be transmitted. When the lines match, the write address set by the write controller is released.
According to still an additional aspect of the present invention, the common buffer memory, the write control table and the read control table are constituted by an external memory.
According to a still further aspect of the present invention, the write controller comprises:
a register in which are sequentially set data indicating a destination line for the transmission of the ATM cell which is read by the read controller;
a bit map generator for reading an ATM cell written at the same address in the common buffer memory, and for generating a bit map which designates a transmission destination line;
a comparator for performing a comparison of the bit map generated by the bit map generator with a corresponding highway line in the write control table, for which the same write address has been set; and
a controller for, upon receipt of the result of the comparison, feeding back to the register the data indicating which transmission destination highway line has been read for the ATM cell, or for clearing the contents of the write control table.
Other objectives and features of the invention will become apparent during the course of the following explanation of the preferred embodiment of the present invention.